Please use this identifier to cite or link to this item:
Title: FPGA implementation of product accumulate codes
Authors: Koh, Tiong Aik
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2009
Source: Koh, T. A. (2009). FPGA implementation of product accumulate codes. Master’s thesis, Nanyang Technological University, Singapore.
Abstract: Product accumulate (PA) codes are a class of low density parity check (LDPC)-like codes with a well defined structure, which allows flexible rate and length adaptation while maintaining good bit error rate (BER) performance. Compared to turbo codes, they provide similar performance but with significantly less decoding complexity and with a lower error floor. This thesis presents our study on the various design tradeoffs needed for the field programmable gate array (FPGA) implementation of PA codes and on the actual FPGA implementation of the PA type I encoder and decoder (codec).
Description: 129 p.
DOI: 10.32657/10356/47030
Schools: School of Electrical and Electronic Engineering 
Rights: Nanyang Technological University
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

Files in This Item:
File Description SizeFormat 
EEE_THESES_80.pdf15.69 MBAdobe PDFThumbnail

Page view(s)

Updated on Jul 17, 2024

Download(s) 20

Updated on Jul 17, 2024

Google ScholarTM




Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.