dc.contributor.authorKoh, Tiong Aiken_US
dc.date.accessioned2011-12-27T05:56:06Z
dc.date.accessioned2017-07-23T08:34:05Z
dc.date.available2011-12-27T05:56:06Z
dc.date.available2017-07-23T08:34:05Z
dc.date.copyright2009en_US
dc.date.issued2009
dc.identifier.citationKoh, T. A. (2009). FPGA implementation of product accumulate codes. Master’s thesis, Nanyang Technological University, Singapore.
dc.identifier.urihttp://hdl.handle.net/10356/47030
dc.description129 p.en_US
dc.description.abstractProduct accumulate (PA) codes are a class of low density parity check (LDPC)-like codes with a well defined structure, which allows flexible rate and length adaptation while maintaining good bit error rate (BER) performance. Compared to turbo codes, they provide similar performance but with significantly less decoding complexity and with a lower error floor. This thesis presents our study on the various design tradeoffs needed for the field programmable gate array (FPGA) implementation of PA codes and on the actual FPGA implementation of the PA type I encoder and decoder (codec).en_US
dc.rightsNanyang Technological Universityen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineeringen_US
dc.titleFPGA implementation of product accumulate codesen_US
dc.typeThesisen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.contributor.supervisorGuan Yong Liangen_US
dc.description.degreeMASTER OF ENGINEERING (EEE)en_US


Files in this item

FilesSizeFormatView
EEE_THESES_80.pdf16.06Mbapplication/pdfView/Open

This item appears in the following Collection(s)

Show simple item record