Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/47034
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dc.contributor.authorLaw, Chong Fatten
dc.date.accessioned2011-12-27T05:56:28Zen
dc.date.available2011-12-27T05:56:28Zen
dc.date.copyright2008en
dc.date.issued2008en
dc.identifier.citationLaw, C. F. (2008). Design methodologies for low-power asynchronous-logic digital systems. Doctoral thesis, Nanyang Technological University, Singapore.en
dc.identifier.urihttps://hdl.handle.net/10356/47034en
dc.description250 p.en
dc.description.abstractAsynchronous design has been an active area of research since the 1950s, but has hitherto yet to achieve widespread use or acceptance. This is largely because several major problems continue to persist that inhibit its acceptance in the very large-scale integration industry as a viable alternative to the prevalent synchronous design. This thesis addresses one such problem: how to reduce the circuit area and power dissipation of asynchronous control networks.en
dc.rightsNanyang Technological Universityen
dc.subjectDRNTU::Engineering::Electrical and electronic engineeringen
dc.titleDesign methodologies for low-power asynchronous-logic digital systemsen
dc.typeThesisen
dc.contributor.supervisorJoseph Changen
dc.contributor.supervisorGwee Bah Hweeen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen
dc.description.degreeDOCTOR OF PHILOSOPHY (EEE)en
dc.identifier.doi10.32657/10356/47034en
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