dc.contributor.authorLaw, Chong Fatten_US
dc.date.accessioned2011-12-27T05:56:28Z
dc.date.accessioned2017-07-23T08:34:05Z
dc.date.available2011-12-27T05:56:28Z
dc.date.available2017-07-23T08:34:05Z
dc.date.copyright2008
dc.date.issued2008
dc.identifier.citationLaw, C. F. (2008). Design methodologies for low-power asynchronous-logic digital systems. Doctoral thesis, Nanyang Technological University, Singapore.
dc.identifier.urihttp://hdl.handle.net/10356/47034
dc.description250 p.en_US
dc.description.abstractAsynchronous design has been an active area of research since the 1950s, but has hitherto yet to achieve widespread use or acceptance. This is largely because several major problems continue to persist that inhibit its acceptance in the very large-scale integration industry as a viable alternative to the prevalent synchronous design. This thesis addresses one such problem: how to reduce the circuit area and power dissipation of asynchronous control networks.en_US
dc.rightsNanyang Technological Universityen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineeringen_US
dc.titleDesign methodologies for low-power asynchronous-logic digital systemsen_US
dc.typeThesisen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.contributor.supervisorJoseph Chang
dc.contributor.supervisorGwee Bah Hweeen_US
dc.description.degreeDOCTOR OF PHILOSOPHY (EEE)en_US


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