Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/47034
Title: Design methodologies for low-power asynchronous-logic digital systems
Authors: Law, Chong Fatt.
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2008
Source: Law, C. F. (2008). Design methodologies for low-power asynchronous-logic digital systems. Doctoral thesis, Nanyang Technological University, Singapore.
Abstract: Asynchronous design has been an active area of research since the 1950s, but has hitherto yet to achieve widespread use or acceptance. This is largely because several major problems continue to persist that inhibit its acceptance in the very large-scale integration industry as a viable alternative to the prevalent synchronous design. This thesis addresses one such problem: how to reduce the circuit area and power dissipation of asynchronous control networks.
Description: 250 p.
URI: http://hdl.handle.net/10356/47034
Rights: Nanyang Technological University
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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