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|Title:||Measuring and characterizing sub-micron MOSFETs||Authors:||Lin, Hong.||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits||Issue Date:||2000||Abstract:||In this thesis, a semi-empirical IDS - VDS model for sub-micron Lightly-Doped Drain (LDD) MOSFETs is proposed with an improvement in the strong inversion region. The proposed model is based on the principle of the conventional n-channel enhancement mode MOSFET by taking into consideration the various phenomena associated with the LDD structure for very short channel MOSFFET devices. The important short-channel device features: Drain-Induced-Barrier-Lowering (DIBL), Channel-Length Modulation (CLM), mobility degradation, velocity saturation, the source/drain parasitic resistance etc. have been considered in the proposed model.||URI:||http://hdl.handle.net/10356/4704||Rights:||Nanyang Technological University||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
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