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|Title:||Customizable instruction cache hierarchy for embedded systems||Authors:||Kugan Vivekanandarajah||Keywords:||DRNTU::Engineering::Computer science and engineering::Hardware::Memory structures||Issue Date:||2005||Source:||Kugan, V. (2005). Customizable instruction cache hierarchy for embedded systems. Doctoral thesis, Nanyang Technological University, Singapore.||Abstract:||Cache hierarchy bridges the ever increasing performance gap between the fast processing core and slow main memory. In an effort to improve the total system performance, the high performance microprocessor designers commit more and more transistor budget for cache memory systems. As a result, power consumption of cache memory subsystems has been increasing notably over each processor generation. Although a number of cache optimization techniques to reduce power consumption have been reported in the literature, power consumption in cache memories is a major concern and accounts for as much as 50% of the total processor power. Since the instruction cache consumes the majority of this power, predictor based schemes have been proposed for the instruction cache hierarchy in an attempt to provide for an overall reduction in the energy delay product.||Description:||146 p.||URI:||https://hdl.handle.net/10356/47483||DOI:||10.32657/10356/47483||Rights:||Nanyang Technological University||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||SCSE Theses|
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