dc.contributor.authorKugan Vivekanandarajahen_US
dc.date.accessioned2011-12-27T08:25:54Z
dc.date.accessioned2017-07-23T08:29:26Z
dc.date.available2011-12-27T08:25:54Z
dc.date.available2017-07-23T08:29:26Z
dc.date.copyright2005
dc.date.issued2005
dc.identifier.citationKugan, V. (2005). Customizable instruction cache hierarchy for embedded systems. Doctoral thesis, Nanyang Technological University, Singapore.
dc.identifier.urihttp://hdl.handle.net/10356/47483
dc.description146 p.en_US
dc.description.abstractCache hierarchy bridges the ever increasing performance gap between the fast processing core and slow main memory. In an effort to improve the total system performance, the high performance microprocessor designers commit more and more transistor budget for cache memory systems. As a result, power consumption of cache memory subsystems has been increasing notably over each processor generation. Although a number of cache optimization techniques to reduce power consumption have been reported in the literature, power consumption in cache memories is a major concern and accounts for as much as 50% of the total processor power. Since the instruction cache consumes the majority of this power, predictor based schemes have been proposed for the instruction cache hierarchy in an attempt to provide for an overall reduction in the energy delay product.en_US
dc.rightsNanyang Technological Universityen_US
dc.subjectDRNTU::Engineering::Computer science and engineering::Hardware::Memory structuresen_US
dc.titleCustomizable instruction cache hierarchy for embedded systemsen_US
dc.typeThesisen_US
dc.contributor.schoolSchool of Computer Engineeringen_US
dc.contributor.supervisorThambipillai Srikanthanen_US
dc.description.degreeDOCTOR OF PHILOSOPHY (SCE)en_US
dc.identifier.doihttps://doi.org/10.32657/10356/47483


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