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|Title:||Design space exploration for algorithm analysis and hardware architecture optimization||Authors:||Saurav Bhattacharyya||Keywords:||DRNTU::Engineering::Computer science and engineering::Theory of computation::Analysis of algorithms and problem complexity||Issue Date:||2006||Source:||Saurav, B. (2006). Design space exploration for algorithm analysis and hardware architecture optimization. Master’s thesis, Nanyang Technological University, Singapore.||Abstract:||Designing embedded systems products is an increasingly challenging proposition due to multiple functional and non-functional constraints posed to design architects. Amongst non-functional constraints, the non-recurring engineering cost (NRE) and time to market (TTM) take a high precedence in decisions to be taken at the design and development stage. Further, due to the increased complexity of designs, and the yawning productivity gaps, designing products to meet specific design points in the area-time-power tradeoff analysis has become a difficult balancing act.||Description:||149 p.||URI:||https://hdl.handle.net/10356/47486||DOI:||10.32657/10356/47486||Rights:||Nanyang Technological University||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||SCSE Theses|
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