dc.contributor.authorSaurav Bhattacharyyaen_US
dc.date.accessioned2011-12-27T08:26:11Z
dc.date.accessioned2017-07-23T08:29:27Z
dc.date.available2011-12-27T08:26:11Z
dc.date.available2017-07-23T08:29:27Z
dc.date.copyright2006
dc.date.issued2006
dc.identifier.citationSaurav, B. (2006). Design space exploration for algorithm analysis and hardware architecture optimization. Master’s thesis, Nanyang Technological University, Singapore.
dc.identifier.urihttp://hdl.handle.net/10356/47486
dc.description149 p.en_US
dc.description.abstractDesigning embedded systems products is an increasingly challenging proposition due to multiple functional and non-functional constraints posed to design architects. Amongst non-functional constraints, the non-recurring engineering cost (NRE) and time to market (TTM) take a high precedence in decisions to be taken at the design and development stage. Further, due to the increased complexity of designs, and the yawning productivity gaps, designing products to meet specific design points in the area-time-power tradeoff analysis has become a difficult balancing act.en_US
dc.rightsNanyang Technological Universityen_US
dc.subjectDRNTU::Engineering::Computer science and engineering::Theory of computation::Analysis of algorithms and problem complexityen_US
dc.titleDesign space exploration for algorithm analysis and hardware architecture optimizationen_US
dc.typeThesisen_US
dc.contributor.researchCentre for High Performance Embedded Systemsen_US
dc.contributor.schoolSchool of Computer Engineeringen_US
dc.contributor.supervisorThambipillai Srikanthan (SCE)en_US
dc.description.degreeMASTER OF ENGINEERING (SCE)en_US


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