Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/47495
Title: Low power reconfigurable digital filter banks for multi-standard wireless communications receivers
Authors: Kavallur Pisharath Gopi Smitha
Keywords: DRNTU::Engineering::Computer science and engineering
Issue Date: 2010
Source: Kavallur, P. G.S. (2010). Low power reconfigurable digital filter banks for multi-standard wireless communications receivers. Doctoral thesis, Nanyang Technological University, Singapore.
Abstract: The fundamental idea of software defined radio (SDR) is to replace most of the analog signal processing in the transceivers with digital signal processing in order to provide the advantage of flexibility through reconfiguration. The digital front-end of an SDR employs a filter bank channelizer to extract individual radio channels from the wideband input signal. Since the filter bank operates at the highest sampling rate in the digital front-end of the receiver, low power and high-speed architectures are required for its implementation. The compatibility of a filter bank channelizer with different communication standards is guaranteed by its reconfigurability. Realizing reconfigurable channelizers with low complexity, low power and high-speed is a challenging task. This thesis addresses the research problem of incorporating low power, high-speed and reconfigurability into the filter bank channelizer architecture for the wideband receiver of an SDR.
Description: 181 p.
URI: https://hdl.handle.net/10356/47495
DOI: 10.32657/10356/47495
Rights: Nanyang Technological University
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:SCSE Theses

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