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https://hdl.handle.net/10356/4801
Title: | Design of high-speed low-power clock and data recovery circuit | Authors: | Alper, Cabuk | Keywords: | DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits | Issue Date: | 2006 | Source: | Alper, C. (2006). Design of high-speed low-power clock and data recovery circuit. Doctoral thesis, Nanyang Technological University, Singapore. | Abstract: | In this thesis, the design of fully integrated high-speed low-power clock and data recovery (CDR) circuits in complementary metal-oxide-semiconductor (CMOS) devices for synchronous optical network (SONET) applications has been explored. | URI: | https://hdl.handle.net/10356/4801 | DOI: | 10.32657/10356/4801 | Schools: | School of Electrical and Electronic Engineering | Rights: | Nanyang Technological University | Fulltext Permission: | open | Fulltext Availability: | With Fulltext |
Appears in Collections: | EEE Theses |
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File | Description | Size | Format | |
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EEE-THESES_8.pdf | 2.41 MB | Adobe PDF | View/Open |
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