Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/4801
Title: Design of high-speed low-power clock and data recovery circuit
Authors: Alper, Cabuk
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2006
Source: Alper, C. (2006). Design of high-speed low-power clock and data recovery circuit. Doctoral thesis, Nanyang Technological University, Singapore.
Abstract: In this thesis, the design of fully integrated high-speed low-power clock and data recovery (CDR) circuits in complementary metal-oxide-semiconductor (CMOS) devices for synchronous optical network (SONET) applications has been explored.
URI: https://hdl.handle.net/10356/4801
DOI: 10.32657/10356/4801
Rights: Nanyang Technological University
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

Files in This Item:
File Description SizeFormat 
EEE-THESES_8.pdf2.41 MBAdobe PDFThumbnail
View/Open

Google ScholarTM

Check

Altmetric


Plumx

Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.