dc.contributor.authorAlper, Cabuken_US
dc.date.accessioned2008-09-17T09:59:01Z
dc.date.accessioned2017-07-23T08:32:01Z
dc.date.available2008-09-17T09:59:01Z
dc.date.available2017-07-23T08:32:01Z
dc.date.copyright2006en_US
dc.date.issued2006
dc.identifier.citationAlper, C. (2006). Design of high-speed low-power clock and data recovery circuit. Doctoral thesis, Nanyang Technological University, Singapore.
dc.identifier.urihttp://hdl.handle.net/10356/4801
dc.description.abstractIn this thesis, the design of fully integrated high-speed low-power clock and data recovery (CDR) circuits in complementary metal-oxide-semiconductor (CMOS) devices for synchronous optical network (SONET) applications has been explored.en_US
dc.rightsNanyang Technological Universityen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
dc.titleDesign of high-speed low-power clock and data recovery circuiten_US
dc.typeThesisen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.contributor.supervisorYeo, Kiat Sengen_US
dc.description.degreeDOCTOR OF PHILOSOPHY (EEE)en_US


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