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|Title:||Design of phase locked loop with PVT tolerance||Authors:||Chong, Kok Foong||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits||Issue Date:||2012||Source:||Chong, K. F. (2012). Design of phase locked loop with PVT tolerance. Master’s thesis, Nanyang Technological University, Singapore.||Abstract:||This thesis proposes a VCO compensation technique that could reduce the VCO’s frequency variation across different PVT conditions. The technique incorporates a simple process variation detection circuit, a comparison circuit that generates digital control codes to control the current that goes to the biasing circuitry of the VCO. The compensation circuitry is of small area and does not consume significant extra power. To verify the proposed compensation techniques in VCO design, a fully-integrated PLL clock generator has been designed for 1GHz~3GHz general purpose clock generation using IBM’s 0.13µm CMOS 8RF process. With proper selection of the compensation currents (and resistors), the usable frequency range could be extended by a factor of 1.45. For the same targeted frequency, the variation of the compensated KVCO is slightly above 10% at most, reduced from a high value of 60% without compensation. Overall, the bandwidth variation is reduced by a factor of 1.7 from 2.2 for a PLL with compensated VCO, for the whole frequency tuning range, across all the PVT variation from -40°C to 125°C. Specifically, for the same targeted frequency, the KVCO variation has been reduced from a factor of 1.6 to about 1.1. For the same target frequency, the maximum variation in damping factor has been reduced from about 1.3 to slightly over 1.05. The frequency variation with respect to the same control voltage is reduced to ±3.9% across all the PVT variation from -40°C to 125°C. VCO dummies are normally added to the VCO in order to provide a uniform loading for each VCO delay stage. To check the impacts of different VCO dummy implementation on PLL jitter, five experimental charge pump PLLs are simulated with difference only in the dummy stages: (i) no dummy, (ii) simple dummy, (iii) single stage differential dummy, (iv) double stage differential dummy and (v) full differential dummy with the D2S converters. The simulation result shows that with the improved symmetry, the noise contributed by the fluctuation in the VCO bias would have been suppressed correspondingly. As a result, the PLL output clock jitter could be reduced by increasing the symmetry in the VCO dummies. However, there is a tradeoff for the jitter performance with the power consumption and silicon area.||URI:||https://hdl.handle.net/10356/48093||DOI:||10.32657/10356/48093||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
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Updated on Feb 27, 2021
Updated on Feb 27, 2021
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