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|Title:||Electrical design, modelling and optimization of a low-cost wafer level chip scale package (WL-CSP)||Authors:||Low, Hong Guan.||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Microelectronics||Issue Date:||2003||Abstract:||This report presented the design of a Wafer Level Chip-Scale Package (WL-CSP) using a patented UTAC’s Build Up (UBU) technology, which is a low-cost packaging process with a redistribution layer. From various papers, it had been shown that WL-CSP has superior electrical performance over conventional and advanced packages.||URI:||http://hdl.handle.net/10356/4811||Rights:||Nanyang Technological University||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
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