Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/48176
Title: Ultra low power cmos phase-locked loop frequency synthesizers
Authors: Vamshi Krishna Manthena
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2011
Source: Manthena, V. K. (2011). Ultra low power cmos phase-locked loop frequency synthesizers. Doctoral thesis, Nanyang Technological University, Singapore.
Abstract: With the increasing demand for low cost and high integration of wireless transceiver building blocks, the low-power performance is a great concern for radio-frequency integrated circuit (RFIC) designers. Intensive effort has been made to develop RF integrated circuits and systems in the gigahertz range using the low-cost CMOS process. The commonly used frequency synthesizer based on the phase-locked loop (PLL) is an important building block of the transceiver. The frequency synthesizer, which performs the main role of carrier generation for the down-conversion/up-conversion operations, is a major and critical block of a wireless transceiver because it operates at high frequency and consumes a very large portion of the total power consumption in the transceiver. The performance in power consumption and channel selection of frequency synthesizer are limited by the two most important building blocks, namely the voltage-controlled oscillator (VCO) and the high frequency divider. The objective of this research work is to design the critical blocks for the frequency synthesizer with low power consumption. In this thesis, we have carried a detailed analysis on the speed and power consumption of the digital dividers and developed low power prescalers based on the dynamic logic. A CMOS fully programmable 1 MHz resolution divider for Zigbee and IEEE 802.15.4 applications is implemented based on pulse-swallow topology which uses the proposed ultra-low power 2/3 prescaler, low power 47/48 prescaler and a reloadable D flip-flop for the counters. A detailed design of wide-band 2/3 prescaler based on dynamic logic is presented which is suitable for IEEE 802.11 a/b/g applications and also verified in the design of fully programmable Multi-band divider which provides flexible resolution.
URI: https://hdl.handle.net/10356/48176
DOI: 10.32657/10356/48176
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

Files in This Item:
File Description SizeFormat 
PHD Thesis_Final copy_Ultra Low Power CMOS PLL Frequency Synthesizers_VamshiKrishna.pdfMain Article5.71 MBAdobe PDFThumbnail
View/Open

Page view(s) 50

388
Updated on Jul 27, 2021

Download(s) 5

493
Updated on Jul 27, 2021

Google ScholarTM

Check

Altmetric


Plumx

Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.