Cu metallization and dielectric removal for failure analysis of ICs

Abstract

Although a defect may be well understood electrically in the recent years, capturing the anomaly into image remains necessary to verify the defect location. As technology further develops, ICs nowadays have more than one interconnect layer. Hence, it is necessary to first remove the overlying layers, otherwise viewing of the embedded defects would be impossible. However, in some cases, the removal of one layer can act as an in-situ decoration of another layer, masking the defect or removing the defect. Thus, it is important that the delayering (also known as parallel lapping) method only removes the unwanted layer.

The main focus of this project is to study the side effect of deprocessing technique for 65 nm copper chip focusing on polishing methodology.

There are two known issues with polishing and they are, inability to achieve a 100% success rate and edge effects which affect the overall planarity of the sample. Edge effect can be caused by several factors such as long polishing times, excessive application of pressure or force, improper usage of slurry with wrong type of polishing cloth, sample is being lowered too much into the polishing cloth.

In the experiments, the polisher was set with two different polishing modes which include oscillation with rotation and oscillation only. The purpose is to find out which of the mode would give a lesser edge effect. Moreover, the effect of the polishing duration and force applied on the sample during polishing as well as the introduction of sacrificial layers will be investigated.

Optical images of the Cu chip were captured during the delayering process and FIB was also used to quantify the thicknesses of the layer stacks for analysis. After analyzing the results obtained from the experiments, it was found that polishing the sample with oscillation mode only and adding sacrificial to samples do help in minimizing edge effect at long polishing times.