Compact modeling of gate-all-around silicon nanowire MOSFETs
Date of Issue2012
School of Electrical and Electronic Engineering
Nanoscience and Nanotechnology Cluster
This thesis documents the compact model development for the silicon nanowire MOSFET. A surface-potential based scalable model is developed for silicon nanowire MOSFET. An accurate surface potential initial guess is derived for the iterative surface potential solution within a few iteration steps. An analytical single-piece expression of the surface potential solution is derived in all regions of operation. An intrinsic long channel transistor drain current model is developed as the core model without charge-sheet approximation. To extend the core model into short channel devices, many physical phenomena including mobility degradation, channel length modulation, velocity saturation, and drain induced barrier lowering are incorporated into the core model. Some threshold voltage definitions are discussed and a new threshold voltage expression is proposed for silicon nanowire MOSFETs. The threshold voltage roll-off, subthreshold slope degradation, and drain induced barrier lowing effects are modeled with an approximate solution of the 2D Poisson’s equation. A simple, accurate, and continuous charge and capacitance model is developed based on the single-piece drain current model. The terminal charges are calculated using Ward-Button partition and the capacitances are obtained by the derivative of the terminal charges with respect to terminal voltages. The channel thermal noise model is developed, in which the thermal noise is obtained by integrating the output conductance along the channel. A novel flicker noise model that includes both mobility fluctuation and carrier fluctuation is developed. An analytical single-piece drain current mismatch model is developed to model the random fluctuation in the device parameters.
DRNTU::Engineering::Electrical and electronic engineering::Nanoelectronics