Design and implementation of a reconfigurable fuzzy inference processor
Date of Issue2006
School of Electrical and Electronic Engineering
To achieve real-time performance for some applications of fuzzy systems, it is necessary to realize the inference module in hardware. By the same token, real time applications of evolvable fuzzy hardware (EFH) systems require the realization of systems as hardware that can be conveniently reconfigured. A good example of such a scenario is illustrated for the case of Asynchronous Transfer Mode (ATM) cell scheduling. Since the domain rule set is expected to evolve during normal operations, it is imperative that the hardware supporting the fuzzy reasoning should be easily reconfigurable. To address this requirement, a reconfigurable fuzzy inference processor (RcFIP) that supports online rule set reconfigurability is proposed in this project. The overall methodology of designing EFH systems based on the RcFIP as the core inference processor is presented in this thesis. The concept of a RcFIP-based intrinsic EFH can be viewed as a type of evolvable hardware (EHW). The RcFIP is an in-system context-switchable inference processor for evolvable fuzzy hardware. A context refers to a situation or scenario of an application requiring specific domain knowledge. In particular, the focus is on the class of applications involving embedded fuzzy control. The domain knowledge therefore refers to fuzzy rules and membership functions. The kind of applications being considered is real time in nature, which necessitates the implementation of the fuzzy inference in hardware. The chip architecture is described and details on the design of the chip is presented in this thesis. The proposed RcFIP which achieves 17M fuzzy logic inference per second (FLIPS) is able to offer high execution speed for time-critical applications. It is a good candidate to develop a multi-task fuzzy inference processor (MtFIP) that is capable of performing multiple tasks or applications concurrently. The development of a MtFIP is another contribution of this project. The detailed hardware architecture of the MtFIP is addressed in this thesis.
DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems
Nanyang Technological University