Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/49433
Title: 16-bit full adder design based on cadence full-custom IC design flow
Authors: Yan, Aung Win
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2012
Abstract: This report represents the implementation of full custom IC design for 16-bit Full Adder. Full Adder circuits are basic block circuits, used not only in the arithmetic logic unit(s), but also in other parts of the processor, where they are used to calculate addresses, table indices, and similar. Those basic logic Adder circuit largely depends on the individual transistors sizing which dominate the power consumptions and delay signal. The technology used in this report is 0.13m IBM technology. The schematics and layouts of typical CMOS logic cells, like Inverter, NAND and EXOR, are designed using with Mentor Graphics tools: Design Architect-IC & IC Station and also designed using with CADEBCE design tool. After the individual cells‘ layout is developed, Design Rule Check (DRC) and Layout versus Schematic (LVS) check are perform to ensure free of errors for final circuit using with Mentor Graphics Calibre tool. The parasitic capacitance extraction has been done using the same tool. After that the post layout simulation is performed. One-bit full Adder circuit, Four-bit full adder circuit and 16-bit full adder circuits are developed using with FPGA Advantage tools and VHDL coding. The functionality and test result are being analyzed.
URI: http://hdl.handle.net/10356/49433
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

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