Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/4953
Title: Low power adiabatic CMOS circuits
Authors: Ng, Kim Wee.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Semiconductors
Issue Date: 2000
Abstract: Power consumption has become a critical concern in the design of digital CMOS circuits. While long being neglected, the topic of low power digital design has vaulted to the forefront of the attention in recent years. This thesis reports on the design of a new class of circuits which can overcome the CV^2f barrier faced by the conventional CMOS logic. Known as the adiabatic or energy recovery logic, it uses the technique of recovering energy that would otherwise be dissipated as heat in order to reduce the power dissipation in digital CMOS circuits. To achieve that, ramp-like power clock signals are required to power-up the circuits. In addition, it does not require a specialized MOS fabrication process (unlike other low power approaches such as that of ultra-low threshold voltage and supply).
URI: http://hdl.handle.net/10356/4953
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

Files in This Item:
File Description SizeFormat 
EEE-THESES_936.pdf
  Restricted Access
13.76 MBAdobe PDFView/Open

Google ScholarTM

Check

Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.