Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/49677
Title: Study of degradation mechanisms in SiON gate dielectric film subjected to negative bias temperature instability (NBTI) stress
Authors: Kang, Chun Wei.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Microelectronics
Issue Date: 2012
Abstract: Negative Bias Temperature Instability (NBTI) on thin and thick PMOS with SION oxide is examined using measurement methods with different measurement delays. UFS method with 100ns delay per measurement point which is the fastest NBTI measurement to-date, Slow measurement with 40µs delay per measurement point and DC measurement with the slowest 5s delay per cycle are used together with 2 different characterization machines to prove that Recoverable component (R) observed during dynamic NBTI exhibits a repeatable trend and is independent of device gate length and oxide thickness under nominal DNBTI condition. Although there are numerous research on NBTI, Reaction-Diffusion model (R-D model) that was used to explain NBTI mechanism previously is shown to be unable to explain the entire picture of NBTI especially from dynamic experiment point of view. It has been shown in our work that hydrogen transport across gate oxide is not the main mechanism for generation of bulk oxide traps. With the focus on the R component in NBTI, another model the 2-stages model is reviewed. A decrease in R component at high temperature still cannot be completely explained by this model. The cyclic behavior of NBTI is ascribed to the behavior of switching hole trap and a decrease in R at high temperature is found to be related to the transformation of fraction of these recoverable oxide vacancy defects, recoverable E' center to permanent E' center. And, we have shown that stress-induced leakage current shares the same defect origin with the switching hole trap related to NBTI. Gate leakage current remains the same before and after nominal NBTI condition when no transformation of E’ center occurs although interface traps has been significantly generated. However, a significant increase in the gate leakage occurs when there is a decrease in R at T=200°C. Lastly, Electrostatic Discharge (ESD) breakdown on PMOS and switching hole traps of NBTI is found to be related as well. ESD experiment is conducted not using the conventional Transmission Line Pulse (TLP) machine but the new Very Fast Transmission Line Pulse (VFTLP) machine which can give out pulse as short as 1ns. A comparable trend of ESD breakdown voltage is observed when the amount of switching hole traps remain constant while the breakdown voltage becomes generally lower when transformation of recoverable recoverable E' center to permanent E' center happened for NBTI experiment at 200°C. A bigger spread in Weibull distribution plot agrees that formation of permanent E' center will thin down the gate oxide. Hence, less traps are needed to form the percolation path that leads to breakdown.
URI: http://hdl.handle.net/10356/49677
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

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