Ultra low-power design techniques for content addressable memory (CAM)

Abstract

Content addressable memory (CAM) is an important component for high performance search operations, used in many applications such as pattern matching, database engines and networking IP address lookup. However, conventional CAM designs consume a large amount of power, thus preventing the implementation and usage of large density CAM in a single chip. Different design methods have been proposed to achieve low power consumption while achieving high speed searching.

This report presents a low matchline voltage swing CAM to achieve low power consumption. Additional features to detect and correct matchline sensing errors were included in the design of the CAM. A 128x128 CAM array was implemented using a 65nm, 1.2V CMOS process. Post-layout simulation results showed that the CAM was able to achieve a 2ns search time using 0.7696fJ/bit/search.