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|Title:||ASIC implementation of a high speed data scaler for residue number system||Authors:||Chay, Chien Hong.||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits||Issue Date:||2012||Abstract:||Unconventional number system, the Residue Number System (RNS) is introduced for its efficient arithmetic operations such as addition, subtraction and multiplication as long operations are broken down into several shorter and independent operations without carry propagation between them. However, scaling, an essential operation in digital signal processing remained as one of the bottleneck of RNS which hinder the wider adoption of RNS due to its non-weighted characteristic.In this project, the architecture of the new proposed scaling algorithm for the programmable scaler is coded and synthesized. The placement and routing of this new RNS design, combining with other designs is also performed using the Cadence® SoC Encounter™ RTL-to-GDSII System version 8.1. Lastly, testing circuitry is also developed to test the functionality of the chip after being fabricated.||URI:||http://hdl.handle.net/10356/49912||Rights:||Nanyang Technological University||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Student Reports (FYP/IA/PA/PI)|
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