A full-custom IC design flow low power design using 16-bit full adder

Abstract

As speed increases and size decreases, power dissipation per unit area is on the rise. Power dissipation became a glaring issue in IC design. Therefore, it draws down the need to learn full custom IC Electronic Design Automation (EDA). The study focuses on processes in full custom design flow in Cadance EDA based on 0.35μm technology. Comparisons were made between two 16-bit full adders of the same transistor count, 28T CMOS complementary full adder and mirror full adder. These adders were created with the implementation of full custom design flow (back end design) to project low power consumption. Simulations were carried out to determine the cause and effect of design techniques on four factors, namely, propagation delay, power consumption, power delay product (PDP) and area. Mirror full adder has outperformed the complementary full adder in all aspects.