Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/4997
Title: Design of low-power and low-voltage VLSI multipliers
Authors: Ong, Geok Ling.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2004
Abstract: This thesis proposes several designs for low-power low-voltage digital CMOS multipliers for two's complement multiplication.
URI: http://hdl.handle.net/10356/4997
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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