Watermark insertion and detection through embedded test machine for VLSI IP protection

Abstract

IP watermarking is an efficient and economical approach to IP protection. In this project, a rather simple testability-driven partitioning method for large gate-level circuits is used for watermarking. The algorithm decomposes a single machine into an interconnection of component machines, each having a constant number of flip-flops. Watermark bits are inserted by incorporating the test function into each component. This method of decomposing a large machine into small components and incorporating testability in each component substantially reduces the time complexity of synthesis. The algorithm is verified and the partition is implemented in C++ program.