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https://hdl.handle.net/10356/50141
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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Che, Xuerong. | |
dc.date.accessioned | 2012-05-30T04:14:05Z | |
dc.date.available | 2012-05-30T04:14:05Z | |
dc.date.copyright | 2012 | en_US |
dc.date.issued | 2012 | |
dc.identifier.uri | http://hdl.handle.net/10356/50141 | |
dc.description.abstract | IP watermarking is an efficient and economical approach to IP protection. In this project, a rather simple testability-driven partitioning method for large gate-level circuits is used for watermarking. The algorithm decomposes a single machine into an interconnection of component machines, each having a constant number of flip-flops. Watermark bits are inserted by incorporating the test function into each component. This method of decomposing a large machine into small components and incorporating testability in each component substantially reduces the time complexity of synthesis. The algorithm is verified and the partition is implemented in C++ program. | en_US |
dc.format.extent | 72 p. | en_US |
dc.language.iso | en | en_US |
dc.rights | Nanyang Technological University | |
dc.subject | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits | en_US |
dc.title | Watermark insertion and detection through embedded test machine for VLSI IP protection | en_US |
dc.type | Final Year Project (FYP) | en_US |
dc.contributor.supervisor | Chang Chip Hong | en_US |
dc.contributor.school | School of Electrical and Electronic Engineering | en_US |
dc.description.degree | Bachelor of Engineering | en_US |
item.fulltext | With Fulltext | - |
item.grantfulltext | restricted | - |
Appears in Collections: | EEE Student Reports (FYP/IA/PA/PI) |
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File | Description | Size | Format | |
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eA2020-111.pdf Restricted Access | 2.02 MB | Adobe PDF | View/Open |
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