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Title: Electrical characterization of the novel vertical slit field-effect transistor (VeSFET)
Authors: Tung, Zhi Yan.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electric power
Issue Date: 2012
Abstract: A junctionless Vertical Slit Field-Effect Transistor (VeSFET) fabricated on SOI wafer using conventional CMOS process was proposed by W. Maly, et al.[1]. This new architecture device has two symmetrical independent gates with a three-dimensional channel. This device structure is to overcome the challenges faced in scaling down the size of transistor, such as short-channel effect faced by conventional MOSFET.
Schools: School of Electrical and Electronic Engineering 
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

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