Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/50254
Title: Design of the low-voltage CMOS analog multiplier
Authors: Guo, Lizao.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2012
Abstract: Analog multipliers have wide range of applications in analog signal processing. Multiplying two real-time analog signals is an important operation in filter, mixer and modulator designs. With the shrinking size of transistor and the increasing demand for low-power devices, it is required to design analog multipliers compatible with low supply voltage. The CMOS analog multiplier has been proposed in many configurations but low-voltage low-power CMOS analog multiplier is still a challenging subject in Integrated Circuit design today. In this thesis, a four quadrant CMOS analog multiplier with 1V supply voltage is presented utilizing the 0.18um process technology. The multiplier is capable of accepting 200mV peak-to-peak input voltage at both input ports and has good linearity within this input range.
URI: http://hdl.handle.net/10356/50254
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

Files in This Item:
File Description SizeFormat 
Design of the Low-voltage CMOS Analog Multiplier.pdf
  Restricted Access
2.84 MBAdobe PDFView/Open

Page view(s) 50

224
checked on Oct 28, 2020

Download(s) 50

16
checked on Oct 28, 2020

Google ScholarTM

Check

Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.