Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/50266
Title: Gate dielectric surface modification in organic field-effect transistors
Authors: Feng, Chengang
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Semiconductors
Issue Date: 2012
Source: Feng, C. (2012). Gate dielectric surface modification in organic field-effect transistors. Doctoral thesis, Nanyang Technological University, Singapore.
Abstract: Organic semiconductors attract intensive research interest because of their unique properties, such easy fabrication, mechanically flexibility, and low cost. They are now widely used as active elements in optoelectronic devices including light-emitting diodes, thin-film field-effect transistors, solar cells and memories, among which organic field-effect transistors (OFETs) offer a suitable building block for many flexible, large-area applications such as display backplanes, electronic textiles, and robotic skin. Interestingly enough, OFETs grew in parallel with another device, the organic light-emitting diode (OLED). However, the development of OLEDs has been much faster than that of OFETs, so that commercial products based on OLEDs are now available on the market, which is not yet the case for OFETs. In the past few years, much research effect has been directed at improving the charge-carrier mobility by better materials and device architectures, subsequently, OFETs are able to match, and in some cases even exceed, the basic transistor performance of amorphous silicon (a-Si) thin-film transistors (TFTs). As OFETs are now moving closer to applications, their operational stability and the control of threshold voltage becomes more crucial than ever. In this thesis, we primarily focus on engineering the interface between organic semiconductor and gate dielectric by dielectric surface modification, which play a decisive role in the functioning of OFET devices, in a top contact bottom gate structure that avoids the influence of the interaction metal contact and the active layer. The work contained in this thesis is firstly directed toward studying the effect of buried traps at dielectric-dielectric interface on the device stability. Hysteresis-negligible pentacene FET devices were demonstrated in the dark condition by using PVP-co¬-PMMA to modify the surface of SiO2 gate insulator. However, the threshold voltage of such devices still can be greatly shifted due to the charge trapping mechanism (minority carrier) by the application of a gate bias under illumination. It suggested that the negligible hysteresis might originate from the dynamic balance of trapping/detrapping charge carriers in our devices. Therefore, it can be concluded that only the demonstration of hysteresis-free FET devices is not nearly enough, one still needs trying to reduce the possibility of charge trapping, or even eliminate it. In order to minimize the charge trapping at the interface between semiconductor and gate dielectric, highly purified PMMA was utilized to substitute PVP-co¬-PMMA as buffer dielectric because of the absence of hydroxyl groups acting as traps. When a thin PMMA buffer dielectric (10 nm) was used, the photo-generated non-equilibrium electrons (holes) in pentacene (C60) active layer near the dielectric surface can also be injected into the buried traps at the surface of SiO2 passivated by thin PMMA layer, inducing the shift in threshold voltage. By understanding the charge trapping mechanism, such photo-induced charge transfer can be effectively suppressed with optimized thickness of PMMA (45 nm) buffer dielectric, thus, stabilize the threshold voltage. This work also shows that besides the device encapsulation and the development of new organic semiconductors (OSCs) combining high mobility with excellent stability, data presented in this work brings out an alternative approach to enhance the stability of OFET devices using dual gate dielectric and a guide about how to select a proper buffer dielectric. From a scientific perspective, it is also very interesting to study the mechanism of charge transfer across a buffer dielectric. For the low-voltage FET devices (operating at 1 V), 12 nm high-κ materials hafnium oxide (HfO2) was used as gate insulator, which was grown on silicon substrate by atomic layer deposition at a temperature of 250 ℃. In this work, the effect of oxygen plasma treatment at the HfO2 surface upon the device performance was thoroughly investigated under atmospheric dark condition. With proper exposure time (t_e), not only mobility but also the stability of devices was improved, attributing to the ultraclean surface of HfO2 with lower concentration of oxygen vacancies and increased grain size of pentacene film. A mobility of 0.056 cm^2 V^(-1) s^(-1) with a threshold voltage of -0.23 V was achieved at t_e=15 s. The subthreshold slope decreased with increasing t_e and a minimum value of 157 mV decade^(-1) was obtained. However, pentacene film on plasma-treated HfO2 was more fragile due to the surface stress enhanced weathering effect. Moreover, oxygen plasma treatment also offers the good tunability of the threshold voltage, as compared to other surface modifications using HMDS, OTS and cross-linked PVP as buffer dielectric that would increase the threshold voltage by lowering the gate capacitance, as the thickness of used low dielectric OTS and cross-linked PVP is comparable to, even larger than that of ALD grown HfO2. This thesis also demonstrates the heterostructure FET devices with a polymeric light-emitting material, crystallized PFO or amorphous PVK, buffer layer. These hole-transport polymers were chosen to form a type I hetero-junction (straddling gap) with pentacene in a FET structure, to study the electronic structure of their interface as well as the charge transport along and charge transfer across such interface, which also can be considered as a complement to the semiconductor-dielectric system such as PVA/P3AT and/or Parylene/rubrene. The heterostructure devices exhibit a typical p-channel operation: for low negative V_g, both field induced charges and photo-generated charges could be confined in the channel layer due to the large 〖∆E〗_HOMO; for high negative V_g, holes were expected to be distributed in both layers. Interestingly, the threshold voltage of such devices can be controlled through varying the positive starting source-gate voltage V_(g_start) under illumination due to the trapping of photogenerated electrons in PFO (or PVK) layer and the interface, e.g. by varying V_(g_start) from 60 to 200 V in the off-to-on transfer curve, a total shift in V_th of ca. 137 V was obtained in PFO-FETs, namely, V_th varied from -14.6 to 122.5 V. The trapping of photogenerated charge is also studied in terms of hysteresis behavior. It is found that the hysteresis window ∆V_th was mainly determined by V_g in PFO-FETs, while it was strongly correlated with the value of V_g & V_ds and the sweeping direction of V_g in PVK-FETs, indicating a different charge injection mechanism. However, the maximum ∆V_th exceeded the half of the total sweep range of V_g in both devices, showing their great charge storage ability. Such light-programmable feature might motivate the development of a new type of organic memory devices.
URI: https://hdl.handle.net/10356/50266
DOI: 10.32657/10356/50266
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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