Effect of stress migration on electromigration for nano scale advanced interconnects.
Date of Issue2012
School of Electrical and Electronic Engineering
The interconnect system is a significant part of the integrated circuit because of its function to connect millions of transistors, and routing signals into and out of the chip. Therefore, investigating its reliability is a priority for the industry to ensure that the chip lifetime will meet the requirements. In order to evaluate reliability, tests must be performed under a harsher, but nonetheless representative, environment than those expected under normal use in order to obtain failure statistics in reasonable times. The most common accelerated reliability test for the Cu interconnects is stress migration (SM) and electromigration (EM) test, where they are typically investigated separately. The objective of SM test is to study the metal failure mechanism due to intrinsic thermomechanical stresses. On the other hand, the purpose of EM test is to study the reliability of copper line with respect to electrical current density. Typical accelerated EM testing conditions are at high temperature, i.e., 300-350°C for Cu interconnects. However, the thermal stress at this temperature will be very low because it is closed to stress free temperature of the metal lines, which is around 300°C. As a result, the effect of intrinsic thermal stress on the reliability and lifetime of metal lines is seldom properly accounted for and current reliability projections based on standard EM test algorithms may be an overestimate. However at use condition, we might find that SM and EM could actually co-exist concurrently and have non-negligible contributions to the physics of failure. SM might occur all the time when the chip is working, typically at temperatures around 100-125°C. At the same time, EM might occur due to the electron wind force through the interconnects. Therefore, it is important to understand the interaction of SM and EM since both can play a collective role in causing interconnect failure at chip operating condition. Despite many extensive studies on the stress migration and electromigration reliability, so far there is no study to describe and explain the interaction between these two failure mechanisms. Therefore, there is a great interest to gain some understanding of SM and EM interaction, hence the reliability risk can be more accurately forecasted. Our study is started with the investigation of individual SM and EM reliability of Cu interconnect with dielectric slot. The purpose of this work is to obtain a good understanding of SM and EM behavior, as the basic to study the interaction between these two failure mechanisms. The possible SM and EM failure mechanisms, design and the process integration challenges are discussed. Next, we present a study on SM and EM interaction in lower (MX structure) and upper metal (MX+1 structure) of dual-damascene Cu/low-κ interconnects. It is found that both mechanisms are dependent; statistical analysis shows that EM failure time is affected by the presence of residual stress induced by SM. This effect was more severe in the lower metal. The reliability implication of the residual stress in copper interconnects on the EM is further investigated with various failure analysis techniques and three-dimensional finite element simulation. A failure mechanism model for stress evolution and void formation is proposed to provide insight into the interaction between these two failure mechanisms. This study is further expanded to investigate the effect of stress migration on electromigration activation energy and current density exponent. A simple empirical method to extrapolate the interconnect lifetime accounting for the effect of both SM and EM will be discussed. In addition, we investigated also the influence of SM on other important EM parameters, i.e., permittivity scaling and short length effect, as it is important for the assessment of further technology scaling and interconnect design. Lastly, we carried out experiments in advanced narrow line copper interconnects to study the influence of SM risk on its EM reliability. As opposed to the current understanding that SM is not a concern for the narrow metal lines due to limited availability of vacancies for voiding, we found that SM does have serious wear-out effects. The high intrinsic tensile stress in the line is suspected to be responsible for this early void nucleation. In addition, we developed a Monte Carlo simulation model to estimate the void nucleation and growth time using the EM-only and SM+EM degradation tests.
DRNTU::Engineering::Electrical and electronic engineering::Microelectronics