Back-end-of-line process reliability of advanced semiconductor technology

Abstract

The main objectives of this project are (1) to establish new test procedures for accurate wafer-level characterization of Cu electromigration behavior and low-k dielectric materials, (2) to measure the wafer-level Cu electromigration characteristics and explain them in terms of microstructural change and interfacial phenomena. The effect of copper metal lines on the device lifetime has been studied from the materials engineering point of view, (3) to study how to correlate the wafer-level reliability data with the product reliability. The wafer-level electromigration test results should be consistent with the package-level results, (4) to fully characterize a new low-k dielectric material (Black-diamond) and its influence on the electromigration reliability of the copper metal lines, (5) to identify issues arising in the integration of the backend processes, (6) to propose ideas of how to resolve integration issues resulting from the new low-k dielectric and investigate its applicability to advanced technologies.