Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/5055
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dc.contributor.authorHo, Chiew Nyuk.en_US
dc.date.accessioned2008-09-17T10:18:44Z-
dc.date.available2008-09-17T10:18:44Z-
dc.date.copyright2000en_US
dc.date.issued2000-
dc.identifier.urihttp://hdl.handle.net/10356/5055-
dc.description.abstractVia represents the weakest link in multilevel metallisation for IC devices and oxide etching is inherent in the via opening step. Because of higher bond energies, oxide etching typically uses aggressive ion-enhanced, fluorocarbon-based plasma systems. It relies on the competing influences of polymer deposition and ion bombardment to achieve anisotropic profiles as well as the required selectivity. The mandate that calls for an in-depth understanding of plasma-surface interactions involving in the etching process and its correlation to the process performance drives the project to address the complex issues on this unit process development, materials properties and reliability. Via etching with TiN antireflection coating (ARC) etch-stop was first investigated. Etching gas composition is found to slightly affect the oxide etch rate but significantly alter the photoresist and TiN etch rates. It is the materials originated etching behaviour that causes the selectivity between these materials. These physical characteristics are correlated to the chemical characteristics of the plasma-induced fluorocarbon film. In addition, residue-free via with the application of post-etch cleaning procedures followed by an additional post-clean treatment has been demonstrated. Electrical characterisation shows that reliability and failure mechanisms depend on the interfacial quality and physical geometry of the via rather than the etch feed gases. Both residual contamination and oxidised layer can affect the electrical properties.en_US
dc.format.extent143 p.-
dc.rightsNanyang Technological Universityen_US
dc.subjectDRNTU::Engineering::Materials::Microelectronics and semiconductor materials-
dc.titleStudy of VIA etching for sub-micron device fabricationen_US
dc.typeThesisen_US
dc.contributor.supervisorHigelin, Geralden_US
dc.contributor.schoolSchool of Materials Science & Engineeringen_US
dc.description.degreeMaster of Engineering (SME)en_US
item.grantfulltextrestricted-
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