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|Title:||High-frequency low-power local oscillator generation||Authors:||Miao, Yannan||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits||Issue Date:||2012||Source:||Miao, Y. (2012). High-frequency low-power local oscillator generation. Doctoral thesis, Nanyang Technological University, Singapore.||Abstract:||With rapid development in the area of RF and wireless communication, the interest in frequency synthesizers has grown rapidly in the last few years. Frequency synthesizer is used for local oscillator (LO) generation. In this thesis, our aim is to explore high-frequency low-power LO generation in CMOS technology. We focus on three most power-hungry blocks in a frequency synthesizer, which dominate the total power consumption due to their high-frequency operation, namely voltage-controlled oscillator (VCO), frequency divider and frequency multiplier, as these circuits are the bottleneck to achieve the above mentioned aim. Through reducing their power consumption, the total power consumption of the frequency synthesizer can be reduced significantly. Moreover, the phase noise of the frequency synthesizer is significantly dependent on the VCO and the frequency multiplier. Thus, novel ideas for these circuits are proposed in Chapter 3, Chapter 4 and Chapter 5. Finally, these ideas are implemented in a frequency synthesizer as a design example in Chapter 6. The frequency synthesizer can operate at the 24-GHz Instrument, Scientific and Medical (ISM) band, which can be used for automotive short range radar. With these ideas in these proposed circuits, the proposed frequency synthesizer can have better performances than those previous designs. Firstly, a divide-by-2/3 injection-locked frequency divider (ILFD) is proposed based on a conventional ILFD with a fixed division ratio, which can be used to design a programmable frequency divider in an integer-N phase-locked loop (PLL). As the most critical characteristic in the low-power and high-frequency ILFD, the operation range is analyzed and then its design equations are derived mathematically. Thus, the mutual operation range in both the divide-by-2 and divide-by-3 modes can be optimized. With a power consumption of 3.15 mW, the operation range of the proposed circuit in the divide-by-2 mode is 3.44~5.02 GHz while the operation range in the divide-by-3 mode is 4.28~4.81 GHz. Moreover, the figure of merit (FoM) for the ILFD is 1.527 GHz/mW. Secondly, a dual-band VCO is designed with a VCO stacking on top of an ILFD for a dual-band frequency synthesizer. With a power consumption of 3.2 mW, the tuning ranges of the dual-band VCO's frequency bands are 4.48~5.86 GHz and 2.24~2.93 GHz, respectively. Moreover, the FoM for the upper and lower frequency bands are -187.1 and -190.1 dB, respectively. Thirdly, a ×2 injection-locked frequency multiplier (ILFM) is proposed with high operation frequency and high conversion gain, while has low power consumption. Moreover, the topology of the proposed circuit is analyzed and its design equations for operation range and conversion gain are derived. A ×(3/2) fractional frequency multiplier (FFM) is also proposed based on the novel topology and optimized for its operation range. The proposed FFM also has high conversion gain and low power consumption at high-frequency operation. Finally, a 24-GHz frequency synthesizer is proposed for low-power operation. Contribution and generation of the phase noise in the frequency synthesizer are analyzed in detail. Through the measured results, it is shown that the frequency synthesizer has very low power consumption of 11.86 mW and low phase noise of -104 and -113 dBc/Hz at 1-MHz and 10-MHz offset frequencies, respectively.||URI:||https://hdl.handle.net/10356/50592||DOI:||10.32657/10356/50592||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
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