3D electromigration modeling at the circuit layout level
Date of Issue2012
School of Electrical and Electronic Engineering
Integrated circuit (IC) reliability is of increasing concern in present-day IC technology where the interconnect failures significantly increases the failure rate for ICs with decreasing interconnect dimension and increasing number of interconnect levels. Electromigration (EM) in the interconnects has now become the dominant failure mechanism that determines the circuit reliability. To model the EM reliability of the interconnects in ICs, a 3-dimensional (3D) electro-thermo-structural model as opposed to the conventional current density based 2-dimensional (2D) models is now necessary because ICs are 3D in their actual physical implementation. In this work, we study the EM reliability of the interconnects in ICs using a 3D finite element circuit model. A simplified circuit structure with only the intra-block interconnects is used as an example to show the construction of a 3D finite element model from its 2D IC layout. This modeling method is then used in the analysis of a realistic circuit structure with the inclusion of both intra- and inter-block interconnects. Transient electro-thermo-structural simulations are carried out using both Cadence (a circuit simulator) and ANSYS (a finite element tool). By limiting our study only to EM failure, the current density, temperature and thermo-mechanical stress distributions of the interconnects are computed by considering the heat transfer and Joule heating, and these values are used to compute the atomic flux divergences (AFDs). As the failure time of the interconnects is inversely proportional to its AFD and void nucleates at the location with highest AFD, the EM lifetime and the EM weak spot of the interconnects can be determined from the value and the location of the maximum AFD respectively. The transient temperature changes with the applied electrical loads and the transient thermo-mechanical stress changes with the circuit temperature demonstrated the transient modeling capability of the model at the circuit layout level, and this is an improvement to the conventional 3D EM models at the test structure level. From our simulation results, it is found that at the circuit operation temperature of 90 oC, the location of the maximum AFD is determined by the product of the temperature gradient and the thermo-mechanical stress gradient; while at the EM test temperature of 300 oC, the location of the maximum AFD is determined by the current density. From the simulations performed using different structures, it is observed that the line-via test structure showed the same maximum AFD location as the circuit structure at 300 oC (i.e. at the location with the highest current density). However, due to the incompleteness in the test structure, the temperature gradient distribution and hence the maximum total AFD location of the line-via test structure are different from the circuit structure at 90 oC. The change in the maximum AFD location may cause a wrong interpretation of the EM weak spot location when the test structure is used for data extrapolation in predicting the EM reliability of the entire circuit. From the simulation performed based on a realistic circuit layout (i.e. a low noise amplifier circuit), it is found that the regions with high thermo-mechanical stress gradient can have comparably high AFD values as the regions with high current density and/or high temperature gradient. Ignoring or overlooking this thermo-mechanical stress effects may cause the simulator to miss out some locations with high possibility of EM failures. This again proves the inadequacy of the conventional current density based EM simulators. Modifications to the interconnect structures, surrounding materials, circuit layout and process are carried out based on the EM weak spots identified. The improvements in the EM lifetime for the modified models are as expected and agree with the reported experimental results in literature. This provides validation to the proposed model. Due to the complexity of the model and the constraint in computation memory, the microstructure and back stress effects are not included in the current model. These effects will be considered in our future work.
DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits