dc.contributor.authorNagarajan Raghavan
dc.date.accessioned2012-10-08T04:15:39Z
dc.date.accessioned2017-07-23T08:34:34Z
dc.date.available2012-10-08T04:15:39Z
dc.date.available2017-07-23T08:34:34Z
dc.date.copyright2012en_US
dc.date.issued2012
dc.identifier.citationNagarajan Raghavan. (2012). Statistical characterization and reliability modeling of novel high-K gate dielectric stacks. Doctoral thesis, Nanyang Technological University, Singapore.
dc.identifier.urihttp://hdl.handle.net/10356/50738
dc.description.abstractHigh-κ (HK) dielectric thin films are currently the most suited insulators for complementary metal-oxide-semiconductor (CMOS) technology in the sub-45nm technology nodes. Hafnium-based dielectrics are widely used in both advanced logic and memory device structures. While reliability studies to qualify the metal gate (MG) – HK stacks have been ongoing for the past few years, there are many unresolved issues regarding the physics and statistical nature of the time dependent dielectric breakdown (TDDB) failure mechanism at the front-end. Some of these issues include (a) deciphering the sequence of BD in the dual layer dielectric stack comprising HfO2 and a thin interfacial layer (IL) of SiOx, (b) studying the origin behind the non-Weibull stochastic nature of BD, (c) decoding the reliability of the individual HK and IL layers, (d) studying the role played by grain boundary (GB) microstructural defects (which cause localized non-random trap generation) on the HK BD statistics, (e) investigating the feasibility of a zero interfacial layer (ZIL) device for sub-16nm nodes from a reliability point of view and (f) extrapolating the device level analysis results to circuit level reliability assessment. These issues form the motivation of this doctoral work. We use electrical characterization, statistical and simulation tools along with failure analysis results as a supporting tool to find solutions to all the above issues listed. Our results clearly indicate IL to be the first layer to BD and at circuit level, failure is most likely to occur by multiple uncorrelated IL soft breakdown (SBD) events rather than a single catastrophic hard breakdown. Percolation BD in the IL layer is also found to be localized around the GB defect lines in the HK film as they serve as low activation barrier paths for oxygen vacancy (defect) diffusion. Based on our electrical observations of post-breakdown recovery in MG-HK MIS logic stacks, we have also been able to explain the origin of resistive switching phenomenon in HfO2-based MIM RRAM considering the role of oxygen vacancy and metal nano-filaments. We report the possibility of operating the same RRAM in two distinct independent switching modes depending on the forming / SET compliance and also quantitatively study the retention reliability of the memory stack at low and high resistance states.en_US
dc.format.extent285 p.en_US
dc.language.isoenen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Semiconductorsen_US
dc.titleStatistical characterization and reliability modeling of novel high-K gate dielectric stacksen_US
dc.typeThesis
dc.contributor.researchMicroelectronics Centreen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.contributor.supervisorPey Kin Leongen_US
dc.description.degreeDOCTOR OF PHILOSOPHY (EEE)en_US
dc.contributor.organizationNanyang Technological University (NTU)en_US


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