Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/50750
Title: A CMOS low power ultra wide band(UWB) transceiver
Authors: Chen, Caixia.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic systems
Issue Date: 2012
Source: Chen, C. (2012). A CMOS low power ultra wide band(UWB) transceiver. Doctoral thesis, Nanyang Technological University, Singapore.
Abstract: Abstract The Ultra-wide-band (UWB) radio is an emerging data rate radio technology intended for low transmission power wireless multimedia applications. The significant advantages of this technology are the low power operation, mitigated multi-path fading effects and unique precise position/timing location ability. In a pulse-based UWB system, very short pulses are modulated and transmitted at a very low power level. Hence, it is important to develop the low power UWB Transceiver. The project presents the design and implementation of a single chip CMOS Low Power UWB Transceiver for short range communications. In the UWB transmitter, the most important point is to generate the short pulses in a well-defined bandwidth. A new Gaussian pulse filter is designed to produce an approximated Gaussian pulse train which has a reduced side-lobe frequency spectrum. The two key points in the design of the new transmitter are the low power and the small chip size. The first transmitter was designed for multi-band operations over the frequency range from 3GHz to 5GHz using the Pulse-Amplitude Modulation (PAM) scheme. The design is based on a 0.18-µm CMOS Baseline process. The core layout size is less than 0.2 mm2. The simulation results show that the generated signals satisfy the FCC spectrum mask. The average power consumption is measured 1.97mW at a 1.8 V supply voltage. After the optimization, the power consumption of the transmitter can be reduced to as low as 1.08mW. Subsequently, the transmitter circuit has been modified to enable two selectable modulation schemes PAM and Pulse-Position Modulation (PPM). The average power consumption is less than 2mW for both types of signaling at a 1.8 V supply voltage. Pulses are transmitted at a PRF (Pulse Repetition Frequency) of 52MHz in multiple 520 MHz bandwidth channels equally spaced within the 3-5 GHz UWB lower band. For the receiver, the Low Noise Amplifier (LNA) has been designed for the same frequency band from 3GHz to 5GHz with a variable gain controlled by tuning the bias voltage. After the amplification, the received signal is down converted to the baseband by the quadrature passive mixers where the quadrature local oscillators are implemented using the Series Quadrature VCO (S-QVCO). Simple low pass filters (LPF) are used to filter the high frequency noise at the mixer outputs. In order to synchronize the pulse polarities, the CMOS full wave rectifiers have been used to detect the pulses in I and Q paths which are then combined to recover the detected baseband pulses. The proposed transmitter and receiver have been integrated into a new single chip UWB transceiver. The total die size of the chip is 3.1 mm2. The performance of the transmitter is similar as above. At the gain of 39dB, the receiver consumes 17mA for the 1.8 V supply voltage. The total power consumption of the transceiver is 30.6 mW. The operating frequency of this transceiver is from 3GHz to 5GHz over multiple 500 MHz bands. Overall, this research work focuses on a low power UWB transceiver with small chip area. Theoretical analysis, simulation results and measurement results are presented to verify the analysis and effectiveness of the proposed design. This work has also been published in technical journals and conferences.
URI: http://hdl.handle.net/10356/50750
metadata.item.grantfulltext: restricted
metadata.item.fulltext: With Fulltext
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