Please use this identifier to cite or link to this item:
Title: Analysis and reduction of mismatch in low power sub-threshold silicon neurons
Authors: Sun, Shuo
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2012
Source: Sun, S. (2012). Analysis and reduction of mismatch in low power sub-threshold silicon neurons. Master’s thesis, Nanyang Technological University, Singapore.
Abstract: In this thesis, we describe a methodical approach for reducing errors due to mismatch in neuron circuits. We chose the neuron’s current-frequency (f-i) curve as the desired output and use a sensitivity analysis to determine which transistors contribute most significantly to its variation. This allows us to identify the most critical transistors that need to be matched. For the special case in which floating-gate (FG) transistors are used to reduce this mismatch, we propose a method to further reduce the number of FG devices to be used in the circuit resulting in a corresponding reduction in ‘calibration’ time. In addition to reducing mismatch between neurons, the usage of FG devices allows the user to independently set the parameters of each neuron. Since the calibration is based on f-i curve, it can be obtained through address-event representation (AER) circuits that are included in the neuron array for normal functionality. We use one example of commonly used integrate and fire neuron to illustrate this mismatch correction procedure. The method presented allows the corrected neurons to compute both rate codes and spike time codes in a mismatch resilient fashion. We have fabricated a chip containing three different type neuron arrays, synaptic circuits, and input/output AER interfacing circuits. It occupies 2.5mmx5.5mm area using VIS 0.35um technology. The chip receives and generates data in AER format, which is asynchronous and digital. However, its internal operation is based on analog low-current circuit techniques.
DOI: 10.32657/10356/51101
Schools: School of Electrical and Electronic Engineering 
Research Centres: VIRTUS IC Design Centre of Excellence 
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

Files in This Item:
File Description SizeFormat 
TeG1002555K.pdf1.52 MBAdobe PDFThumbnail

Page view(s) 50

Updated on Jun 23, 2024

Download(s) 10

Updated on Jun 23, 2024

Google ScholarTM




Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.