dc.contributor.authorSun, Shuo
dc.date.accessioned2013-01-14T03:26:29Z
dc.date.accessioned2017-07-23T08:34:41Z
dc.date.available2013-01-14T03:26:29Z
dc.date.available2017-07-23T08:34:41Z
dc.date.copyright2012en_US
dc.date.issued2012
dc.identifier.citationSun, S. (2012). Analysis and reduction of mismatch in low power sub-threshold silicon neurons. Master’s thesis, Nanyang Technological University, Singapore.
dc.identifier.urihttp://hdl.handle.net/10356/51101
dc.description.abstractIn this thesis, we describe a methodical approach for reducing errors due to mismatch in neuron circuits. We chose the neuron’s current-frequency (f-i) curve as the desired output and use a sensitivity analysis to determine which transistors contribute most significantly to its variation. This allows us to identify the most critical transistors that need to be matched. For the special case in which floating-gate (FG) transistors are used to reduce this mismatch, we propose a method to further reduce the number of FG devices to be used in the circuit resulting in a corresponding reduction in ‘calibration’ time. In addition to reducing mismatch between neurons, the usage of FG devices allows the user to independently set the parameters of each neuron. Since the calibration is based on f-i curve, it can be obtained through address-event representation (AER) circuits that are included in the neuron array for normal functionality. We use one example of commonly used integrate and fire neuron to illustrate this mismatch correction procedure. The method presented allows the corrected neurons to compute both rate codes and spike time codes in a mismatch resilient fashion. We have fabricated a chip containing three different type neuron arrays, synaptic circuits, and input/output AER interfacing circuits. It occupies 2.5mmx5.5mm area using VIS 0.35um technology. The chip receives and generates data in AER format, which is asynchronous and digital. However, its internal operation is based on analog low-current circuit techniques.en_US
dc.format.extent93 p.en_US
dc.language.isoenen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Electronic circuitsen_US
dc.titleAnalysis and reduction of mismatch in low power sub-threshold silicon neuronsen_US
dc.typeThesis
dc.contributor.supervisor2Arindam Basuen_US
dc.contributor.researchVIRTUS IC Design Centre of Excellenceen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeMASTER OF ENGINEERING (EEE)en_US
dc.contributor.organizationVIRTUS, Integrated Circuit Design Centre of Excellenceen_US


Files in this item

FilesSizeFormatView
TeG1002555K.pdf1.560Mbapplication/pdfView/Open

This item appears in the following Collection(s)

Show simple item record