Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/51690
Title: Low-power and robust SRAM design
Authors: Chen, Junchao.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2013
Abstract: This thesis pertains to the design of low power and robust SRAMs without significant area overhead and speed penalty. Novel designs are presented to reduce the power dissipation by using dynamic voltage scaling as well as reducing the power dissipation on large capacitive metal lines, for example bitlines. Robustness is enhanced by using asynchronous Quasi-Delay-Insensitive (QDI) technique to reduce the possible synchronous failure in conventional synchronous counterpart, by using novel memory cells to reduce the read and write stability problem in conventional SRAMs as well as by using efficient bit-interleaved structure to increase the soft-error immunity when combined with error correction code (ECC).
URI: http://hdl.handle.net/10356/51690
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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