Low-power and robust SRAM design

Abstract

This thesis pertains to the design of low power and robust SRAMs without significant area overhead and speed penalty. Novel designs are presented to reduce the power dissipation by using dynamic voltage scaling as well as reducing the power dissipation on large capacitive metal lines, for example bitlines. Robustness is enhanced by using asynchronous Quasi-Delay-Insensitive (QDI) technique to reduce the possible synchronous failure in conventional synchronous counterpart, by using novel memory cells to reduce the read and write stability problem in conventional SRAMs as well as by using efficient bit-interleaved structure to increase the soft-error immunity when combined with error correction code (ECC).