Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/51690
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dc.contributor.authorChen, Junchao.
dc.date.accessioned2013-04-08T07:46:34Z
dc.date.available2013-04-08T07:46:34Z
dc.date.copyright2013en_US
dc.date.issued2013
dc.identifier.urihttp://hdl.handle.net/10356/51690
dc.description.abstractThis thesis pertains to the design of low power and robust SRAMs without significant area overhead and speed penalty. Novel designs are presented to reduce the power dissipation by using dynamic voltage scaling as well as reducing the power dissipation on large capacitive metal lines, for example bitlines. Robustness is enhanced by using asynchronous Quasi-Delay-Insensitive (QDI) technique to reduce the possible synchronous failure in conventional synchronous counterpart, by using novel memory cells to reduce the read and write stability problem in conventional SRAMs as well as by using efficient bit-interleaved structure to increase the soft-error immunity when combined with error correction code (ECC).en_US
dc.format.extent77 p.en_US
dc.language.isoenen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Integrated circuitsen_US
dc.titleLow-power and robust SRAM designen_US
dc.typeThesis
dc.contributor.supervisorGwee Bah Hweeen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeMaster of Engineeringen_US
dc.contributor.researchCentre for Integrated Circuits and Systemsen_US
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