Please use this identifier to cite or link to this item:
|Title:||Low power asynchronous digital signal processor||Authors:||Shi, Yiqiong.||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Electronic systems::Signal processing||Issue Date:||2012||Abstract:||This thesis pertains to the design of a digital signal processor (DSP) with emphasis on lowpower for power-sensitive applications such as battery-operated embedded systems. The low-power attribute is largely obtained by means of exploiting the idiosyncrasies of asynchronous-logic, an emerging design methodology with intrinsic fine-grain clock gating and improved average-case performance (compared to the competing prevalent synchronouslogic approach). The specific asynchronous-logic modality adopted is the single-rail bundled-data approach, and the specific DSP is the fixed-point 24-bit Motorola DSP56000, a somewhat dated DSP but whose architecture remains largely contemporary. This thesis describes the complete design and, in part, the monolithic realization (130nm CMOS) of an asynchronous-logic DSP56000 and its contemporary synchronous-logic counterpart. The purpose of the latter DSP is largely for benchmarking. The monolithic realization includes the Data Arithmetic Logic Unit (DALU) of both DSPs, one of the most complex blocks of the DSP. To realize the low-power attribute of the asynchronous DSP, several novel designs are proposed and state-of-the-art practices adopted. First, the novel architectural features proposed for the asynchronous DALU include employing asynchronously-controlled edge-sensitive flip-flops to resolve potential data hazards and to mitigate redundant switching, grouping of instructions according to their delays and assignment of appropriate fast-reset delay elements thereto, the design of a novel configurable block-level completion tree for higher performance, and assignment of low Vt and high Vt cells according to an ‘essential-path’ optimization. Benchmarking on the basis of measurements on prototype ICs shows that the power dissipation of the proposed asynchronous DALU is substantially reduced (>40% lower power) compared to its synchronous counterpart, while its average speed is comparable.||URI:||http://hdl.handle.net/10356/52419||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.