Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/52489
Title: New architectures of multiplier and inner-product processor for high-speed on-chip serial-link bus
Authors: Meher, Manas Ranjan.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2013
Abstract: Research activities in bit-serial arithmetic circuits have been saturated in recent years due to the unprecedented throughput demand in today's electronic applications that is difficult to achieve even by the parallel counterparts. In addition, the area advantage of serial architecture is becoming insignificant due to technology scaling. However, with the rapid increase in integration density of Intellectual Properties (IPs) and application modules in a single System-on-Chip (SoC) to cater for a wide range of applications, the on-chip parallel communication has been severely affected due to routing complexity and power dissipation of interconnects. To eliminate this problem, recent attempts have been made to reduce the number of on-chip parallel channels by introducing the serial-link bus architecture. The serial-link bus architecture establishes bit-serial communication among the on-chip modules at several Giga bits per second (Gbps). With this new approach, serial architectures could find a new set of applications if they are able to process the data at ultra high frequency. The primary goal of this work is to investigate the bit serial implementation of commonly used arithmetic circuits such as accumulator, multiplier and multiply-and-accumulate (MAC) units capable of directly sampling and processing serial-link data at Gbps without buffering. The thesis presents a novel approach that utilizes simple binary counters in designing accumulators, multipliers, inner-product units and discrete cosine transform (DCT) processors. The conventional full adder (FA) used in these circuits are functionally replaced by 1's counter circuit to significantly boost up the sampling frequency of these bit-serial arithmetic circuits.
URI: http://hdl.handle.net/10356/52489
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

Files in This Item:
File Description SizeFormat 
TeG0600261L.pdf
  Restricted Access
4.53 MBAdobe PDFView/Open

Google ScholarTM

Check

Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.