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|Title:||Sample-and-hold circuits for ultra-high-speed analog-to-digital converters||Authors:||Huang, Jiong.||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits||Issue Date:||2013||Abstract:||Implemented in front of the comparator arrays, the sample-and-hold (S/H) or track-and-hold (T/H) circuits are indispensable for high-speed analog-to-digital converters (ADCs) to minimize the aperture error and fully exploit their speed potential, by keeping the input signal of the comparators constant for a sufficiently long period to settle their output values. As the performance of the S/H circuits determines the overall performance of the data acquisition systems, stringent requirements are imposed on them in terms of speed and accuracy. Hence, the S/H circuits are often deemed as the design bottle-neck. Under low supply voltages, there is substantial tradeoff among bandwidth, signal swing, distortion, noise, chip area, and power consumption. Particularly, as the open-loop architecture is chosen over its closed-loop counterpart to achieve high throughput, input-dependent distortions are fully exposed. For sampling switches, the most frequently used components, the causes of these distortions, like the on-resistance modulation, the channel charge injection (CCI), the sampling instant variation and the hold-mode feedthrough, are identified and stressed. Since they can hardly be removed by the preceding circuitry, the nonlinear distortions should be minimized in the S/H circuits. There are numerous techniques developed to cope with these artifacts, but they ought to meet the speed requirement of the S/H circuits. In this dissertation, three basic open-loop S/H topologies are studied, namely, switched-capacitor (SC), switched-source follower (SSF) and series sampling (SS); the innate features of each are reviewed. To enhance the performance while sustaining high speed, innovative modifications are tailored to each topology, instead of employing any cumbersome techniques. For the SC-based T/H circuits, the sampling rate is mainly determined by the rate of the formation and removal of the channel of the sampling switch, and thus can be very high. The modified gate bootstrapping technique is proposed to regulate the on-resistance of the sampling switch without seriously affecting the sampling rate. However, the sampling switch alone cannot drive any capacitive load, so input/output buffers have to be implemented. The novel source follower (SF) buffers are proposed that feature the error compensation and bandwidth enhancement technique; they facilitate resolution up to 7.5 bits at the sampling rate of 4 giga-samples per second (GSPS) according the simulation results. The other two kinds of S/H circuits accommodate larger signal swing and have the hold-mode feedthrough removed. They have the capacitive level shifters implemented in front of the SSFs to develop gate voltages in excess of the supply voltage, fully exploit the signal swing capability of SFs, and facilitate ultra-low voltage operation. Reference voltages are deliberately designed to obtain the desired level shifting value. During the hold mode, the parasitic signal path is shorted to ground, and the feedthrough phenomenon is suppressed. Unlike the conventional techniques for hold-mode feedthrough removal, e.g. a T-switch, the proposed S/H circuits exhibit a wider bandwidth and much larger load driving capability in the tracking mode. The simulation results indicate that these S/H circuits can achieve a sampling rate up to 2.5GSPS. Featuring distinct advantages, these three kinds S/H circuits will fulfill the different specifications of various high-speed applications, especially high-speed ADCs.||URI:||http://hdl.handle.net/10356/52549||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
Updated on Nov 25, 2020
Updated on Nov 25, 2020
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