Design a power-efficient asyncrhonous logic quasi-delay-insensitive network-on-chip for multi-core processor

Abstract

This report pertains to the design of a power-efficient asynchronous logic quasi-delay-insensitive (QDI) Network-on-Chip (NoC) for multi-core processor. To achieve the low power requirement, the proposed NoC is designed to operate in the sub-threshold region. However, operating in the deep sub-threshold voltage region is challenging. In the sub-threshold region, extreme variations (Process, Voltage and Temperature, PVT) are present and increasingly so when nano-scaled fabrication processes are employed. To accommodate these PVT variations, four custom Static Logic Transistor-level Implementation (SLTI) cells are designed and implemented in asynchronous QDI logic using STMicroelectronics (STM) 65nm CMOS process. Delay-insensitive (DI) circuits make no assumption on gate and wire delays, making it very robust to PVT variations. Circuits that are DI, which makes no assumption on the delay of gates and wires, with the exception for carefully identified wire forks labelled as isochronic are called QDI. The SLTI cells are characterized and have achieved lower power dissipation of 13% - 59% lower power, as well as higher speed of 0% - 115% compared to Weak-Condition Half Buffer (WCHB) implementation.

The proposed NoC is designed for a 3 × 3 mesh topology, uses wormhole routing, with a flit size of 18 bits, quad-rail encoding and deterministic order routing (DOR). The proposed NoC supports two virtual channels (VCs) which reduces head-of-line blocking by providing two queues in the NoC. Simulations have shown that the proposed NoC is indeed QDI, robust to PVT variations and workable in the sub-threshold region. In addition, it dissipates at least 80% lesser power, requires 70% lesser energy per flit and occupies 84% lesser area with a setback of at most 18% in speed as compared to other asynchronous QDI NoCs.