Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/53206
Title: Schottky barrier engineering on dopant-segregated schottky silicon nanowire MOSFETs
Authors: Chin, Yoke King
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2010
Source: Chin, Y. K. (2010). Schottky barrier engineering on dopant-segregated schottky silicon nanowire MOSFETs. Doctoral thesis, Nanyang Technological University, Singapore.
Abstract: Silicon nanowire with Gate-All-Around architecture is considered as one of the most promising candidates for CMOS scaling beyond 11 nm technology node due to its superior gate to channel electrostatic control. However, due to the one dimensional nature of nanowire, the resistance at the nanowire source/drain (S/D) extension is inherently high. Nickel silicide (NiSi) Schottky S/D is introduced to address this issue. 2 potential challenges associated with NiSi Schottky S/D are: (1) rapid NiSi intrusion into the silicon nanowire channel during silicidation and (2) the existence of a Schottky barrier which leads to increased contact resistance.
URI: https://hdl.handle.net/10356/53206
DOI: 10.32657/10356/53206
Schools: School of Electrical and Electronic Engineering 
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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