Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/53461
Title: Design of low voltage, 16kb 9T SRAM with hierarchical bitline and writeback block
Authors: Li, Ricky Qi.
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2011
Abstract: Subthreshold circuits are increasingly popular especially in ultra-low power applications like wireless sensor, cell phone, and biomedical where minimal power consumption is a primary design constraint. Static Random Access Memory (SRAM) with wider supply voltage range is essential for achieving better performance as well as minimizing power consumption in subthreshold region.
URI: http://hdl.handle.net/10356/53461
Schools: School of Electrical and Electronic Engineering 
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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