Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/53479
Title: Hardware implementation of optimum channel codes
Authors: Sunish Bharathan.
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2011
Abstract: Applications of signal processing have engendered numerous breakthroughs in science and technology, transforming mundane lifestyles to a whole new dimension of comfort and indulgence that includes mobile broadband, high definition streaming, etc. One important aspect of signal processing that contributed to such luxuries is the channel coding, which is evident in our daily usage, ranging from mobile phone to satellite communications. Recently, a special class of block codes, known as Low Density Parity Check (LDPC) codes, has piqued interest upon many researchers for its capacity approaching performance as well as the speed of its decoding algorithm that transcends most existing channel codes.
URI: http://hdl.handle.net/10356/53479
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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