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|Title:||Nanoscale characterization and analysis of localized degradation and breakdown of high-k dielectric stacks||Authors:||Shubhakar.||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Microelectronics||Issue Date:||2012||Abstract:||Degradation and breakdown of high-κ (HK) dielectrics in advanced complementary metal-oxide-semiconductor (CMOS) technology node is one of the major challenges, due to its polycrystalline microstructure upon post-deposition annealing. Grain boundaries (GBs) in polycrystalline HK dielectrics with a high density of defects, show complex current conduction mechanisms and serve as high leakage paths. Local physical and electrical properties of gate dielectrics affect the overall performance and reliability of the HK based CMOS device. Hence, it is important to study the role of GBs, which have a width of ~1-2 nm, on the reliability and performance of polycrystalline HK dielectrics. As the degradation of HK dielectric and its eventual breakdown (BD) occur locally at the nanoscale, reliability and failure analysis at the “nanometer resolution” becomes very essential to the study of the overall reliability of HK dielectrics. We employ scanning tunneling microscopy (STM), atomic force microscopy (AFM) and transmission electron microscopy (TEM) as the high resolution failure analysis tools for a combined physical and electrical characterization. STM and AFM experiments were carried out at ultra-high vacuum (~10-10 Torr) conditions. The main objectives of this doctoral thesis work are to study (a) the role of GB in polycrystalline HfO2 and CeO2 HK dielectric degradation and BD, (b) localized degradation and BD analysis in nanometer scale induced by STM/AFM and its correlation to the TEM analysis, (c) the effect of lanthanum (La) doping on HfO2 and CeO2 dielectrics and dual layer ZrO2/HfO2 dielectric stack in enhancing the time-dependent-dielectric breakdown robustness. The results clearly reveal faster degradation at GB sites and their vulnerability to early percolation, supporting the phenomenon of GB-assisted HK gate dielectric degradation and breakdown. The STM and C-AFM results on GB are supported by the device and statistical simulation results. Hence, the microstructure of the HK dielectric thin films plays a very significant role in determining the overall reliability of the gate stack. A new technique is adopted to induce the degradation and BD of the HfO2/SiOx dielectric stack locally, using a combined STM/scanning electron microscopy nano-probing system. The study of STM induced localized dielectric degradation and polarity dependent BD in HfO2/SiOx dielectric stacks is presented in this work, together with a correlated investigation of the BD locations by TEM. The analysis of the degradation and breakdown phenomenon has been performed from a macroscopic (device) level to a localized nanometer scale BD location. The BD events were performed on blanket wafers and gate electrode area of the dielectric, and carried out the physical analysis using TEM. This method of analysis is very useful in studying the nature of the BD events in dielectrics with and without the gate electrode, elucidating the role of the gate electrode in dielectric BD events. The results obtained from the localized degradation and BD analysis is in good agreement with the previously reported results on degradation and BD of MOSFET device. Based on the results of last part of the work, an insertion of La2O3 on HfO2 and CeO2, and dual-layer ZrO2/HfO2 are proven to be effective techniques to significantly enhance the reliability and performance of advanced HK dielectric stacks.||URI:||http://hdl.handle.net/10356/53914||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
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