CMOS low power circuits for approximate computer arithmetic

Abstract

Power is an unavoidable and significant issue nowadays in CMOS circuits design. Motivated by chasing for low power to meet the increasing demands of portable devices, this project was focused on low power CMOS circuits. Comparison was done between different full adder designs for approximate computer arithmetic. Analysis of power dissipation, propagation delay, load capacitance and size of transistors are made based on simulation run in Cadence. PDP (power-delay product) was also used to measure the complex performance of different designs. From the simulation results, it was found that decreasing of supply voltage effectively reduced power dissipation. However, low supply voltage will lead to long propagation delay. Six full adders of different design structure were tested and taking advantages of resiliency of output degradation, designs using fewer transistors performed better in PDP metric. Using these imperfect full adders to build compound arithmetic circuits will save power and decrease area for portable devices.