Design of the low-voltage CMOS analog multiplier

Abstract

Analog multiplier is an important device in analog signal processing. It is widely found in many applications such as mixers, filters and oscillators. Since the current trend of Integrated Circuit Design focuses on low voltage and low power, it is desirable to design analog multipliers which can operate in low voltage environment. Although a number of multiplier architectures have been proposed, the CMOS analog multiplier with low voltage and low power features is still a challenging subject in the IC Design field. In this thesis, a four quadrant analog multiplier that operates under 1V supply using 0.18μm CMOS process is presented. The proposed multiplier can accept input voltage from -130mV to 130mV and exhibits good linearity within this range.